1. Field of the Invention
The present invention relates to a process for fabricating semiconductor devices wherein extremely high precision on the location of device components is maintained.
2. Development of the Invention
In current large scale integration (LSI) processing techniques for forming, e.g., bipolar transistors, emitter and isolation formation is performed using two separate photolithographic steps. In electron beam lithography, for example, to maintain a 1 micron space between device components, an inherent alignment error of .+-.0.4 microns with respect to electron beam alignment marks exists with current state of the art technology. Thus, when two alignments are performed, for example one for emitter alignment and one for isolation alignment, a potential error of as great as 0.8 microns can occur. Using current photolithographic techniques, 1.5.mu. spacings can be obtained with an alignment error of .+-.0.6.mu.. In such a situation, using current state of the art technology, the possibility thus exists that the emitter-base junction and isolation will be too close or, alternatively, one or more of these device elements will overlap with one or more other device elements, leading to poor device performance. A further problem is that if the emitter-base junction and isolation are extremely close, i.e., there is high alignment error, high mechanical stresses present near the isolation region after high temperature heat treatments can impact on device performance.
The above situation is illustrated in simplified form in FIG. 1 where substrate 1 is provided with electron beam registration marks 10 and 11 and there is shown emitter 20 and isolation trench 21 in perfect alignment as illustrated by the solid line; however, as illustrated by the broken lines, if emitter 20 is misaligned 0.4 microns to the right and isolation trench 21 is misaligned 0.4 microns to the left, the space separating these two device elements is only 0.2 microns.
U.S. Pat. No. 4,131,497 Feng et al discloses a method of manufacturing self-aligned semiconductor devices. However, in Feng et al there is no isolation/base alignment or emitter alignment as per the present invention; further, emitter size can vary substantially without accurate control, a factor in distinction to the present invention.
U.S. Pat. No. 4,135,954 Chang et al discloses a method for fabricating self-aligned semiconductor devices utilizing selectively etchable masking layers. However, according to the procedure of Chang et al, there is no self-alignment of the emitter and base or alignment with respect to the isolation.
U.S. Pat. No. 4,160,991 Anantha et al discloses a high performance bipolar device and a method for making the same. As with the preceding references, Anantha et al does not disclose a process which would permit isolation/emitter self-alignment.